Electronic signaling within and between integrated circuits (ICs) is accomplished using many different formats, standards, and approaches. Each of these electronic signaling types may be based on and/or reflect a voltage range or swings thereof, an absolute current or changes thereto, a signaling speed or frequency modulation, a combination thereof, and so forth. The various circuits that are used to implement such different electronic signaling types are equally diverse.
Two examples of such diverse circuit types for implementing the different electronic signaling types are (i) current mode logic (CML) circuitry and (ii) low voltage differential signaling (LVDS) circuitry. These two circuit types may be employed as signal output drivers.
FIG. 1 illustrates a conventional current mode logic (CML) type output driver. The conventional CML type output driver is shown as part of a transmitter (Tx). The Tx communicates with a receiver (Rx) over a channel. More specifically, the Tx is in communication with the Rx over the channel via an alternating current (AC)-coupling. This AC-coupling is represented in the channel by the capacitive elements 130 and 135. Capacitive elements 130 and 135 are illustrated as capacitors in FIG. 1.
The CML output driver of the Tx includes two inputs: a negative Tx output circuit input (TOCI (N)) and a positive Tx output circuit input (TOCI (P)). The CML output driver also includes two outputs: positive transmitter output (TP) and negative transmitter output (TN). The Rx includes two inputs: positive receiver input (RP) and negative receiver input (RN).
On the “left” side of the CML output driver, a resistive element 105 is connected in series with a transistor 115 between a supply or high-valued voltage VTT and a current bias 125. Current bias 125 is also coupled to a common potential of the circuit and/or system. Resistive element 105 is illustrated as a resistor, transistor 115 is illustrated as a negative-channel metal oxide semiconductor (NMOS) transistor, and current bias 125 is also illustrated as an NMOS transistor. The current bias is applied by changing or setting the voltage level at the gate terminal of transistor/current bias 125. The TOCI (N) is located at the gate of transistor 115, and the TP is located at a node between resistive element 105 and transistor 115.
On the “right” side of the CML output driver and in parallel with the “left” side, a resistive element 110 is connected in series with a transistor 120 between voltage VTT and current bias 125. Resistive element 110 is illustrated as a resistor, and transistor 120 is illustrated as an NMOS transistor. The TOCI (P) is located at the gate of transistor 120, and the TN is located at a node between resistive element 110 and transistor 120. Differentially-encoded information is applied to the CML output driver at TOCI (N) and TOCI (P).
The Tx at nodes TP and TN is connected across the channel via capacitive elements 130 and 135 to the Rx at inputs/nodes RP and RN, respectively. The Rx is capable of receiving signals, including differentially encoded signals, of a CML type from the CML output driver of the Tx across the channel at nodes RP an RN. A resistive element 140 is connected across nodes RP an RN. Resistive element 140 is illustrated as a resistor.
In the Rx, two resistive elements 145 and 155 are connected in series between voltage VTT and a common potential. Two other resistive elements 150 and 160 are also connected in series between voltage VTT and the common potential. Each of resistive elements 145, 150, 155, and 160 is illustrated as a resistor. Node RP is located between resistive elements 145 and 155. Node RN is located between resistive elements 150 and 160. Node RP is connected to a first input of a differential amplifier 165, and node RN is connected to a second input of differential amplifier 165. Differential amplifier 165 recovers the differentially-encoded information and provides the information at its output.
In operation, the current established by current bias 125 determines the voltage drop across resistive elements 105 and 110. Whether current is flowing across resistive elements 105 and 110 is determined by whether transistors 115 and 120, respectively, are turned on to thereby permit the current established by current bias 125 to flow through the “left” or “right” half of the CML output driver.
When TOCI (N) is at a high voltage, transistor 115 is on and current is flowing across resistive element 105 to drop the voltage seen at node TP. When TOCI (N) is high, TOCI (P) is at a low voltage and transistor 120 is therefore off. When transistor 120 is off, current is not flowing across resistive element 110, and the voltage at node TN is high. These voltage levels at nodes TP and TN are transmitted across the channel to be sensed at nodes RP and RN, respectively, of the Rx and to be interpreted at power amplifier 165. The CML type output driver of the Tx of FIG. 1 operates in an inverse process when TOCI (N) is at a low voltage and TOCI (P) is at a high voltage.
FIG. 2 illustrates a conventional low voltage differential signaling (LVDS) type output driver. The conventional LVDS type output driver is shown as part of a Tx. Although not illustrated in FIG. 2, the Tx may communicate with a Rx over a channel as shown in FIG. 1. However, for typical LVDS type output drivers, the Tx is in communication with the Rx via a direct current (DC)-coupling. Such a DC-coupling between the Tx and the Rx creates a linkage between the common mode (CM) voltage of the Tx and the CM voltage of the Rx. Consequently, the CM voltage of the Tx is usually set and maintained in accordance with the requirements or preferences of the Rx.
The LVDS output driver of the Tx includes two outputs: node TP and node TN. The values of these outputs are determined by the opened and closed positioning of a set of switches, as are described operationally below.
For the LVDS output driver, a collection of switches and resistive elements are connected in series between first and second ideal current sources that are used as push/pull current sources. These current sources may be implemented as one or more transistors. The collection of switches and resistive elements, along with the first and second current sources, are connected in series between a supply or high-valued voltage VTT and a common potential.
The collection of switches and resistive elements includes four switches 215, 220, 225, and 230 and two resistive elements 205 and 210. The two resistive elements 205 and 210 are illustrated as two resistors in FIG. 2. Switch SP 215 is connected in series with switch SN 225 between the two current sources. In parallel with switch SP 215 and switch SN 225, switch SN 220 is connected in series with switch SP 230 between the two current sources.
Node TP is located between switch SP 215 and switch SN 225, and node TN is located between switch SN 220 and switch SP 230. Resistive element 205 is connected in series with resistive element 210. Resistive element 205 is coupled to node TP, and resistive element 210 is coupled to node TN.
During operation of the LVDS output driver, two switch configurations may be implemented as indicated by the two different directions of the arrows. In a first switch configuration, switch SP 215 and switch SP 230 are closed while switch SN 225 and switch SN 220 are open. Consequently, node TP is set to be voltage high, and node TN is set to be voltage low as current flows from node TP to node TN across resistors 205 and 210. In a second switch configuration, on the other hand, switch SN 225 and switch SN 220 are in a closed position while switch SP 215 and switch SP 230 are in an open position. Consequently for this second switch configuration, node TP is set to be voltage low, and node TN is set to be voltage high.
In the first switch configuration, current flows through closed switch SP 215, through resistive elements 205 and 210, and through closed switch SP 230. Because of the voltage drop across resistive elements 205 and 210, node TP may be (e.g., depending on possible voltage drops across the two current sources) approximately equal to voltage VTT while node TN may be approximately equal to VTT minus the product of the current and the sum of the resistance values of resistive elements 205 and 210. In the second switch configuration, current flows through closed switch SN 220, through resistive elements 210 and 205, and through closed switch SN 225. Because of the voltage drop across resistive elements 210 and 205, node TN may be approximately equal to voltage VTT while node TP may be approximately equal to VTT minus the product of the current and the sum of the resistance values of resistive elements 210 and 205.
In other words, for node TP to be voltage high and node TN to be voltage low, switches SP 215 and 230 are closed while switches SN 220 and 225 are open. For node TN to be voltage high and node TP to be voltage low, on the other hand, switches SN 220 and 225 are closed while switches SP 215 and 230 are open. The CM of the LVDS output driver of FIG. 2 corresponds to the voltage potential between resistive element 205 and resistive element 210. Notably, this CM remains relatively constant.
There is no existing approach for combining a CML output driver and an LVDS output driver. Accordingly, there is a need for methods and apparatuses for implementing a multi-mode driver, including schemes and techniques that enable such a multi-mode driver to reproduce respective characteristics of the different drivers for the respective individual modes.